the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibility for in accuracies or ommisions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at t he user?s own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. sirenza microdevices does not authorize or warrant any sir enza microdevices product for use in life-support devices and/or systems. copyright 2006 sirenza microdevices, inc. all worldwide rights reserved. 303 south technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 1 eds-103099 rev g sirenza microdev ices? SGB-6533 is a high performance sige hbt mmic amplifier utilizing a darlington configuration with an active bias network. the active bias network pr ovides stable current over tempera- ture and process beta variations. designed to run directly from a 5v supply the SGB-6533 does not require a drop resistor as compared to typical darlington amplifiers. this r obust amplifier features a class 1c esd rating, low thermal resistance , and unconditional stability. the SGB-6533 product is designed for high linearity 5v gain block applica- tions that require small size and mi nimal external components. it is on chip matched to 50 ohm and an extern al bias inductor choke is required for the application band. this product is available in a rohs compliant and green package with matte tin finish, designated by the ?z? package suffix. key specifications symbol parameters: test conditions z 0 = 50 , v cc = 5.0v, ic = 88ma, t = 30oc) unit min. typ. max. f o frequency of operation mhz dc 3000 s 21 small signal gain ? 850mhz db 25.0 small signal gain ? 1950mhz 17.0 18.5 20.0 small signal gain ? 2400mhz 17.0 p 1db output power at 1db compression ? 850mhz dbm 19.0 output power at 1db compression ? 1950mhz 17.0 18.5 output power at 1db compression ? 2400mhz 18.0 oip3 output ip3 ? 850mhz 32.0 output ip3 ? 1950mhz db 30.0 32.0 output ip3 ? 2400mhz 32.0 irl input return loss @ 1950mhz db 11.0 15.0 orl output return loss @1950mhz db 10.0 14.0 ic current ma 76 88 98 nf noise figure @1950mhz db 3.7 4.7 r th, j-l thermal resistance (junction - lead) oc/w 60 functional block diagram SGB-6533 SGB-6533z dc ? 3 ghz acti ve bias gain block product features applications ? available in lead free, rohs compliant, & green packaging ? high reliability sige hbt technology ? robust class 1c esd ? simple and small size ? p1db = 18.5 dbm @ 1950mhz ? ip3 = 32 dbm @ 1950mhz ? low thermal resistance = 60 c/w ? 5v applications ? lo buffer amp ? rf pre-driver and rf receive path product description vcc nc nc gnd nc nc nc vbias nc nc nc rfin nc rfout nc nc active bias pb rohs compliant & package green
303 south technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 2 eds-103099 rev g SGB-6533 dc-3ghz active bias gain block pin out description pin # function description 1,2,4, 6, 7,8,11, 12,14 nc these are no connect pins. leave them unconnected on the pc board. 3 rfin rf input pin. a dc voltage should not be connected externally to this pin 5 gnd an extra ground pin that is connected to th e backside exposed paddle. connection is optional. 10 rfout rf output pin. bias is applied to the darlington stage thru this pin. 13 vbias this pin sources the current from the active bi as circuit. connect to pin 10 thru an inductor choke. 16 vcc this is vcc for the active bias circuit. back- side gnd the backside exposed paddle is the main electrical gnd an d requires multiple vias in the pc board to gnd. it is also the main thermal path. simplified device schematic 16 1 4 58 9 12 13 15 14 2 3 11 10 67 active bias absolute maximum ratings parameters value unit current (ic total) 150 ma device voltage (v d )6.5v power dissipation 0.75 w operating lead temperature (t l ) -40 to +85 oc rf input power, zload = 50 ohm 15 dbm rf input power, zload > 10:1 vswr 7 dbm storage temperature range -40 to +150 oc operating junction temperature (t j )+150oc operation of this device beyond any one of these limits may cause permanent damage. for re liable continuous operation the device voltage and current must not exceed the maximum operating values specified in the table on page one. bias conditions should also sati sfy the following expression: i d v d < (t j - t l ) / r th? j-l detailed performance table: vcc=5v, ic=88ma, t=25c, z=50ohms symbol parameter units 100mhz 500mhz 850mhz 1950mhz 2400mhz 3500mhz g small signal gain db 28.4 26.9 25.0 18.5 17.0 13.1 oip3 output 3rd order intercept point dbm 32.0 32.0 32.0 32.0 p1db output power at 1db compression dbm 19.1 19.0 18.5 18.0 irl input return loss db 15.1 19.1 26.4 15.0 13.5 8.7 orl output return loss db 21.4 18.5 15.3 14.0 11.9 13.6 s12 reverse isolation db 30.8 30.3 29.7 26.2 25.4 22.9 nf noise figure db 4.6 3.1 3.1 3.7 4.2 4.9 caution: esd sensitive appropriate precaution in handling, packaging and testing devices must be observed.
303 south technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 3 eds-103099 rev g SGB-6533 dc-3ghz active bias gain block evaluation board data (vcc=v bias = 5.0v, i c = 88ma) bias tee is substitu ted for dc feed inductor (l1) ic vs. tem perature 0. 070 0. 075 0. 080 0. 085 0. 090 0. 095 0. 100 0. 105 0. 110 0. 115 0. 120 +85c +25c -40c temperature ic (ma) current vs. voltage 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 0.160 4.44.64.85.05.25.45.65.86.06.2 vc (volts) ic (a) noise figure vs. frequency 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.00.51.01.52.02.53.03.5 frequency (ghz) noise figure (db) +25c +85c -40c p1db vs. frequency 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 0.4 0.9 1.4 1.9 2.4 frequency (ghz) p1db (dbm) +25c +85c -40c oip3 vs. frequency 28.0 29.0 30.0 31.0 32.0 33.0 34.0 0.4 0.9 1.4 1.9 2.4 frequency (ghz) oip3 (dbm) +25c +85c -40c gain vs. frequency 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 0.4 0.9 1.4 1.9 2.4 frequency (ghz) gain (db) +25c +85c -40c
303 south technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 4 eds-103099 rev g SGB-6533 dc-3ghz active bias gain block evaluation board data (vcc=v bias = 5.0v, i c = 88ma) bias tee is substitu ted for dc feed inductor (l1) l s 11 l vs. frequency -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 frequency (ghz) s 11 (db) +25c +85c -40c l s 22 l vs. frequency -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 frequency (ghz) s 22 (db) +25c +85c -40c l s 12 l vs. frequency -35.0 -30.0 -25.0 -20.0 -15.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 frequency (ghz) s 12 (db) +25c +85c -40c l s 21 l vs. frequency 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 frequency (ghz) s 21 (db) +25c +85c -40c
303 south technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 5 eds-103099 rev g SGB-6533 dc-3ghz active bias gain block typical evaluation board schematic for 5.0v rfin rfout vcc nc nc optional gnd nc nc nc vbias nc nc nc rfin nc rfout nc nc vcc c1 c2 c3 c4 l1 1 1 6 1 c3 c2 c1 l1 c4 evaluation board - board material getek, 31mil thick, dk=4.2, 1 oz. copper * c4 is optional depending on application and filtering. not required for sgb device operation. component values by band designator 500mhz 850mhz 1950mhz 2400mhz c3 1000pf 1000pf 1000pf 1000pf c4* 1uf 1uf 1uf 1uf c1, c2 220pf 68pf 43pf 22pf l1 68 nh 33nh 22nh 18nh note: the amplifier can be run from a 8v supply by simply inserting a 33 ohm resistor in series with vcc.
303 south technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 6 eds-103099 rev g SGB-6533 dc-3ghz active bias gain block package outline drawing (dimensions in mm) part number orde ring information part number reel size devices/reel SGB-6533 13? 3000 SGB-6533z 13? 3000 part marking the part will be symbolized with an ?SGB-6533? for sn/pb plating or ?sgb-65z? for rohs green compliant product. marking designator will be on the top surface of the package. recommended land pattern (dimensions in mm[in].): recommended pcb soldermask (smobc) for land pattern(dimensions in mm[in]): 1.58 [0.062] 0.50 [0.020] 0.26 [0.010] 0.38 [0.015] 0.29 [0.011] 0.21 [0.008] 1.58 [0.062] 0.75 [0.030] ?0.38 [?0.015] 0.005 chamfer (8pl) plated thru (4pl) 1.20 [0.047] 0.50 [0.020] 0.25 [0.010] 1.20 [0.047] 0.46 [0.018] 0.53 [0.021] 3.17 [0.125]
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